It is known to manufacture image sensors using CCD technology or CMOS technology. One advantage of CMOS technology is that it allows additional devices to be fabricated directly alongside a photodiode on a semiconductor wafer. A conventional three transistor (3T) Active Pixel Sensor (APS), or active pixel, is shown in FIG. 1. A reset transistor M1 initialises the cathode of a photodiode 11 to a known voltage at the beginning of an image capture. After a reset, radiation incident on the photodiode generates a photocurrent which starts to integrated charge at the gate of a source-follower/buffer amplifier M2. At the end of an image capture, select transistor M3 is enabled to provide an output voltage which is dependent on the amount of charge stored at the gate of transistor M2.
FIG. 2 shows an array 5 of pixels 10, each pixel 10 being of the form just described. The pixels 10 are arranged in a grid of rows and columns. Pixels in each row are connected to a row select line 7. Row selection logic 6 controls signals applied to the set of row SELECT lines 7. Each column of pixels 10 in the array 5 is connected by a column output line 9. In use, rows are selected, one at a time, by enabling respective select lines 7, and the voltage of each pixel in the selected row is output to a respective column output line 9 for processing 8.
In order to be able to fabricate large area CMOS image sensors, the pixels have to be designed with a low sensitivity to defects that occur on the wafer. One type of defect which is particularly problematic is where a row select line 7 erroneously connects to a supply line (VDD), as shown by link 13, or where a row select line 7 erroneously connects to a column output line 9, in region 14. These errors can result from defects in the fabrication process. Defect 13 causes an entire row of pixels 10 to be permanently selected and prevents other rows from being read out. Consequently, the entire array 5 cannot be used. Defect 14 also causes the entire row of pixels to be permanently selected, because column output line will be tied to a high voltage during operation. This prevents the other rows from being read out. Consequently, also for this defect, the entire array can not be used.
One known solution to reduce this problem is described in US2005/051775 and shown in FIG. 3. Two select transistors M4, M5 are arranged in series between transistor M2 and column output line 9. Two row select lines are provided (select line 1, select line 2). Each select transistor M4, M5 is connected to a different one of the row select lines. Now, even if one of the select lines is erroneously connected to supply line VDD, as shown by defect 13, the row will not be selected until the other select line is enabled. This scheme requires one additional transistor per pixel and one additional control line. However, a defect which shorts both select lines to the supply line, shown as 15, will still render the array non-operational. Such double short errors can occur at large defects on a wafer, such as defects of a few microns in size.
The present invention seeks to provide an alternative way of minimising the effects of defects in a pixel array.